1. Field of the Invention
The invention relates to a metal oxide semiconductor (MOS) transistor, a semiconductor device containing the MOS transistor, and to methods of making the MOS transistor.
2. Background of the Invention
Attempts to increase device integration density in microelectronic integrated circuits typically have resulted in the fabrication of smaller and smaller MOS transistors having shorter channels. Decreasing the channel length of the MOS transistors, however, degrades the punch-through characteristics and the drain induced barrier lowering (DIBL) characteristics. Due to this degradation, drain leakage current can flow through the channel even if a sub-threshold voltage is applied to the gate of the MOS transistor. This in turn increases a stand-by current of the semiconductor device that includes short channel MOS transistors. Many mechanisms have therefore been proposed in order to solve this short channel effect.
For example, proposed methods of improving the short channel effect include reducing the thickness of the gate insulating layer, and increasing the doping concentration of the channel. These methods, however, result in the variation of the threshold voltage of the MOS transistor. Accordingly, techniques recently have been developed for forming shallow source/drain regions in order to improve the short channel effect. Forming the source/drain regions too shallow, however, reduces the process margin of over etching for forming contact holes and exposing the source/drain regions. In other words, if the junction depth of the source/drain region is too shallow, it is difficult to control the over etching process for etching an interlayer insulating layer on the shallow source/drain regions.
A method of forming a MOS transistor is described in U.S. Pat. No. 5,843,826 entitled xe2x80x9cDeep submicron MOSFET devicexe2x80x9d by Hong, which is incorporated herein by reference in its entirety. According to Hong, elevated polysilicon patterns are formed on isolation layers at both sides of an active region, and a silicon layer is grown using a selective epitaxial growth technology on the active region and the elevated polysilicon patterns. A MOS transistor then is formed on the epitaxial silicon layer using conventional methods. Accordingly, it is possible to realize elevated source/drain regions extending into the upper regions of the isolation layer. As a result, it is possible to minimize the width of the active region and to concurrently increase the over etching process margin during formation of the contact hole and exposing the source/drain region.
Selective epitaxial growth technology, however, requires very accurate process conditions. For example, surfaces of the underlying material layers, e.g., the active region and the polysilicon layer should be very clean. Thus, it is difficult to form a uniform epitaxial layer on the active region and the polysilicon pattern, in the event that contaminants such as crystal defects due to the etch damages, or native oxide layers exist on the active region or the polysilicon pattern. Thus, a pre-cleaning treatment needs to be performed prior to the epitaxial growing process, which requires very careful attention. Also, according to Hong, it is difficult to minimize the width of the isolation layer under the elevated source/drain region. Accordingly, there are limitations in increasing the integration density using the methods described in Hong.
It is a feature of the present invention to provide simple and less complicated methods for forming MOS transistors, which can increase the over etching process margin of the etching process for forming contact holes and exposing the source/drain regions. It is another feature of the present invention to provide methods of forming MOS transistors that can easily form shallow source/drain regions. It is still another feature of the present invention to provide a MOS transistor having shallow source/drain regions.
These and other features of an embodiment of the present invention may be provided by a MOS transistor including a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type. The insulated gate pattern is disposed so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, and at least one spacer is disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.
In accordance with another feature of an embodiment of the invention, there is provided a method of making a MOS transistor including providing a semiconductor substrate of a first conductivity type, and forming an insulated gate pattern having sidewalls on a predetermined region of the semiconductor substrate of a first conductivity type. The insulated gate pattern is formed so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. Impurity regions of a second conductivity type can be formed on the semiconductor substrate of a first conductivity type at at least one side of the gate pattern, and a first interlayer insulating layer formed on the entire surface of the resultant structure having the impurity regions. The method also includes forming pad contact holes by patterning the first interlayer insulating layer and by exposing at least a portion of the impurity regions, and forming a conformal buffer layer on the entire surface of the resultant structure having the pad contact holes. The method further includes forming at least one pad by patterning the conformal buffer layer, whereby the at least one pad covers at least the impurity regions.
In accordance with other features of an embodiment of the invention, there is provided a method of forming a MOS transistor that includes providing a semiconductor substrate of a first conductivity type, and forming a second conductivity type well at a predetermined region of the semiconductor substrate of a first conductivity type. A first insulated gate pattern having sidewalls and a second insulated gate pattern having sidewalls are formed on a predetermined region of the semiconductor substrate of a first conductivity type, and on a predetermined region of the well, respectively. The first and second insulated gate patterns are formed so that portions of the semiconductor substrate of a first conductivity type on both sides of the first insulated gate pattern remain exposed, and portions of the well on both sides of the second insulated gate pattern remain exposed.
The method also includes forming second conductivity type impurity regions on portions of the semiconductor substrate of a first conductivity type at both sides of the first insulated gate pattern that remain exposed, and forming first conductivity type impurity regions on portions of the well at both sides of the second insulated gate pattern that remain exposed. A first interlayer insulating layer is formed on the entire surface of the resultant structure having the first and second conductivity type impurity regions, and having the first and second insulated gate patterns, and then patterned to form pad contact holes. Forming the pad contact holes exposes the first and second conductivity type impurity regions so that portions of the first interlayer insulating layer remain disposed on the first and second insulated gate patterns.
The method further includes forming a conformal undoped buffer layer on the entire surface of the resultant structure having the pad contact holes and the portions of the first interlayer insulating layer, and ion-implanting second conductivity type impurities in the conformal undoped buffer layer that is disposed on the second conductivity type impurity regions to form a second conductivity type buffer layer. First conductivity type impurities can then be ion-implanted in the conformal undoped buffer layer that is disposed on the first conductivity type impurity regions to form a first conductivity type buffer layer. Sacrificial insulating layer residues can be formed to cover the first and second conductivity type buffer layers on the bottoms of the pad contact holes. The first and second conductivity type buffer layers then can be etched using the sacrificial insulating layer residues as etching masks to form a first conductivity type pad and a second conductivity type pad on the first conductivity type impurity region and on the second conductivity type impurity region, respectively.
These and other features of the invention will be readily apparent to those skilled in the art upon reading the description of preferred embodiments that follows.